System, method and apparatus for memory with embedded associative section for computations
US8332580B2 · kind B2 · utility
4Cited by
7References
88Claims
0Family size
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Key dates
| Filing date | May 13, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Mar 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.