Out-of-order X86 microprocessor with fast shift-by-zero handling
US8332618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Aug 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.