Semiconductor integrated circuit and testing method thereof
US8332662B2 · kind B2 · utility
0Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/0723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.