Scan insertion optimization using physical information
US8332699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.