Using synthesis to place macros
US8332798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.