Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs
US8332802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.