Pixel array with shared readout circuitry
US8334491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Mar 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/46
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.