High speed latch circuit with metastability trap and filter
US8334712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | May 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.