Digital phase detection circuit and method
US8334716B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2009 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Apr 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.