Wear leveling method for non-volatile memory device having single and multi level memory cell blocks
US8335886B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2009 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Oct 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.