Logical map table for detecting dependency conditions between instructions having varying width operand values
US8335912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2009 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used to detect dependencies may be stored in a logical map table, which may include a content-addressable memory. The logical map table may maintain a logical register to physical register mapping, including entries dedicated to physical registers available as rename registers. In one embodiment, each entry in the logical map table includes a first value usable to indicate whether only a portion of the physical register is valid and whether the physical register includes the most recent update to the logical register being renamed. Use of this first value may allow precise detection of dependency conditions, including evil twin conditions, upon an instruction reading from at least two portions of a logical register having an entry in the logical map table whose first value is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.