Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
US8335960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2008 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for ensuring data integrity in a data processing system are disclosed. The method may include monitoring when data for a specified device is available for error correction code generation. A new error correction code may be generated in hardware for the data, based on the indicated size of the data. Detected errors may be corrected in software, based on the generated new error correction code. A first indication of the specified device, a second indication of the data and a third indication of a size of the data may be received during the monitoring. The method may also include indicating when the generating of the new error correction code for a specified number of accesses for at least a portion of the data is complete, and enabling or disabling the error correction code generation. The enabling and/or the disabling may be accomplished via an enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.