Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
US8335977B2 · kind B2 · utility
64Cited by
75References
57Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2008 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.