Computing device and method for inspecting layout of printed circuit board
US8336020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2011 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.