Backside bevel protection
US8338242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2011 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Apr 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.