Surface plasmon enhanced light-emitting diode
US8338819B2 · kind B2 · utility
6Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Nov 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/872
Abstract
A surface plasmon enhanced light-emitting diode includes, from bottom to top, a substrate, an n-type semiconductor layer, a light-emitting layer, a p-type semiconductor layer, and a plurality of metal filler elements. The p-type semiconductor layer includes upper and lower surfaces, and the upper surface is recessed downward to form a plurality of spaced apart recesses for receiving the metal filler elements, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.