Semiconductor memory device including active pillars and gate pattern
US8338873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jan 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/20
Abstract
Provided are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a plurality of active pillars projecting from a semiconductor substrate, a gate pattern disposed on at least a portion of each of the active pillars with a gate insulator interposed therebetween, and a conductive line disposed on each of the active pillars and below the corresponding gate pattern, the conductive line may be insulated from the semiconductor substrate and the gate pattern, wherein each of the active pillars may include a drain region above the corresponding gate pattern, a body region adjacent to the corresponding gate pattern, and a source region that is in contact with the conductive line below the gate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.