Patent · US Active

Configurable digital-analog phase locked loop

US8339165B2 · kind B2 · utility

24Cited by

31References

21Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Jeremy Darren Dunworth · San Diego, US
Gary John Ballantyne · San Diego, US
Bhushan Shanti Asuri · San Diego, US

Key dates

Filing date	Dec 7, 2009
Grant date	Dec 25, 2012
Priority date	—
Expiry date	Feb 27, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/093
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.