Method for improving the performance of the summing-node sampling calibration algorithm
US8339303B2 · kind B2 · utility
2Cited by
4References
65Claims
0Family size
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Key dates
| Filing date | Apr 26, 2011 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Aug 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.