Package substrate
US8339797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package substrate includes a main package body including a first principal surface on which an IC is mounted, and a second principal surface, opposed to the first principal surface, on which first bonding materials for mounting are provided. An internal circuit is provided within the main package body and connected to the first bonding materials. A sub-package is arranged on the second principal surface and includes electronic components embedded therein. A thickness direction dimension being the distance from the second principal surface to a portion of the sub-package most distant from the second principal surface, is not more than a thickness direction dimension being the distance from the second principal surface to an edge of the first bonding material at the second principal surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.