High speed packet interface and method
US8340005B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 19, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.