Architecture using integrated backup control and protection hardware
US8340793B2 · kind B2 · utility
4Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Mar 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/25471
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic control configuration includes at least one secondary microprocessor operable to control a device. The at least one secondary microprocessor assumes protection control of the device responsive to a first type of failure by transmitting a protection control signal to a first effector. The at least one secondary microprocessor assumes backup control of the device responsive to a second type of failure by transmitting a backup control signal to a second effector. The backup control functionality of the at least one secondary microprocessor can be selectively disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.