Methods and apparatus for efficient vocoder implementations
US8340960B2 · kind B2 · utility
1Cited by
6References
12Claims
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Key dates
| Filing date | Jun 16, 2009 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.