R and C bit update handling
US8341379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.