Statistical iterative timing analysis of circuits having latches and/or feedback loops
US8341569B2 · kind B2 · utility
1Cited by
4References
5Claims
0Family size
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Key dates
| Filing date | Jul 23, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.