Controlling depth and latency of exit of a virtual processor's idle state in a power management environment
US8341628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Feb 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.