Method of fabricating thin film transistor by crystallization through metal layer forming source and drain electrodes
US8343796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2011 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Aug 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a thin film transistor includes patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern, forming a gate electrode corresponding to the amorphous semiconductor layer pattern on a gate insulating layer, forming an interlayer insulating layer on the entire surface of the substrate, forming a first contact hole partially exposing the amorphous semiconductor layer pattern, forming a second contact hole partially exposing the gate electrode, and forming a metal layer on the entire surface of the substrate. The method also includes applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern, and patterning the metal layer to form source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.