Anticounterfeiting system and method for integrated circuits
US8344485B1 · kind B1 · utility
2Cited by
4References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2010 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Oct 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit die comprises a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.