Semiconductor structure comprising pillar and moisture barrier
US8344504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2011 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/821
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.