N-bits successive approximation register analog-to-digital converting circuit
US8344931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2011 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Aug 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.