Architecture to facilitate reuse in multiple applications
US8345459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2011 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.