Capacity and density enhancement circuit for sub-threshold memory unit array
US8345468B2 · kind B2 · utility
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8References
3Claims
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Key dates
| Filing date | Aug 18, 2009 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.