Method of setting read voltage minimizing read data errors
US8345487B2 · kind B2 · utility
13Cited by
1References
7Claims
0Family size
Assignee
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Key dates
| Filing date | May 6, 2010 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Mar 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.