Memory system for controlling distribution of packet data across a switch
US8345701B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory system for ingress processing is arranged to access multiple banks in a time interleaved fashion. Each memory bank has an associated memory bank manager, which is arranged to track the contents and egress ports associated with data stored in the memory bank. Incoming data from ingress traffic is evaluated and segregated based on criteria. One of the memory banks is identified based on the criteria, and the incoming data is stored in the identified memory bank in the next available write cycle timeslot. Data constructs in the memory bank manager are updated to indicate the location and egress port associated with the stored data. The memory bank managers submit egress transmit bids to a master scheduler, which controls access to the memory banks. The memory banks are readout in interleaved fashion such that the effective average traffic arrival rate is increased and memory bandwidth requirements are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.