Digital radio processor architecture with reduced DCO modulation range requirement
US8345811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.