Memory device and memory device control method
US8347026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device according to this invention includes: N internal memory read buses and N internal memory write buses each including a plurality of internal slots; N memory modules; an output data bus and an input data bus each including a plurality of external slots; a read data processing unit which (i) selects, from pieces of data read from the N memory modules via the N internal memory read buses, pieces of data read via two or more internal slots, and (ii) provides the selected pieces of data to external slots of the output data bus; and a write data processing unit which provides each of pieces of data provided via the external slots included in the input data bus, to one of the internal slots included in the N internal memory write buses, so as to write the pieces of data to the N memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.