Patent · US Active

Method and semiconductor memory with a device for detecting addressing errors

US8347150B2 · kind B2 · utility

0Cited by

8References

18Claims

0Family size

Assignee

Continental Teves AG & Co. OHG · DE

Inventors

Lukusa Didier Kabulepa · Langen (Hessen), DE
Houman Amjadi · Karlsruhe, DE
Wolfgang Fey · Niedernhausen, DE
Adrian Traskov · Steinbachl, DE

Key dates

Filing date	Dec 5, 2007
Grant date	Jan 1, 2013
Priority date	—
Expiry date	Apr 11, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/1202
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.