Protocol aware error ratio tester
US8347153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Feb 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/323
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with protocol awareness is disclosed. The apparatus comprises of two major blocks: a General Purpose Platform (GPP) and an Analog Front End (AFE). Physical layer testing is divided into two sets of testing procedures: Receiver and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode, or into a more advanced mode where the test system is communicating with the DUT on a protocol level and counts the frame error ratio (FER). This FER is protocol dependent and each protocol receiver has its own way of reporting transmission errors to the transmitter. The protocol awareness of this invention is capable of detecting such a level of errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.