Hierarchical decoding apparatus
US8347194B2 · kind B2 · utility
10Cited by
3References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2009 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/296
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.