Reduced memory multi-channel parallel encoder system
US8347200B1 · kind B1 · utility
3Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 18, 2012 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jun 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/611
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit receives, from the plurality of encoders, respective requests for a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders at staggered times for use in respective encoding operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.