Method of manufacturing a semiconductor device having a super junction
US8349693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2011 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Feb 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
Abstract
A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.