Chip stacked structure and method of fabricating the same
US8350373B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Mar 28, 2011 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.