Hardware synthesis from multicycle rules
US8350594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Mar 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.