Circuit for resetting system and delay circuit
US8350612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset circuit and a delay circuit are provided. The delay circuit includes a first resistor module, a second resistor module, a switch module and a capacitor module. First terminals of the first and the second resistor modules are coupled respectively to a first voltage and a second voltage. The switch module have a control terminal served as a input terminal of the delay circuit, a first terminal served as a output terminal of the delay circuit, a second terminal coupled to a second terminal of the first resistor module, and a third terminal coupled to a second terminal of the second resistor module. In the delay circuit, the first terminal selectively connected to the second terminal or the third terminal in accordance with the control terminal. The capacitor module couples between the first terminal of the switch module and the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.