Level shift circuit
US8351235B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2010 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Jun 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A feedback circuit by which an output of a memory device for storing level-shifted data can be fed back to the input side includes inverters, resistors, and transistors. The resistance value of combined resistance for pulling up or down first and second switching devices is varied in accordance with the output of the memory device by the feedback circuit, so that malfunction caused by dv/dt noise can be dealt with out generating any through current. In this manner, it is possible to provide a level shift circuit which can deal with malfunction causing dv/dt noise regardless of an on or off state of a high-potential-side switching device, while generation of a through current can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.