Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device
US8351263B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Jul 19, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.