Low power dual processor architecture for multi mode devices
US8351985B2 · kind B2 · utility
1Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Jan 20, 2012 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Jan 20, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.