System for providing running digital sum control in a precoded bit stream
US8352826B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2008 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.