High throughput interleaver / deinterleaver
US8352834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2010 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Mar 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2936
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.