Method and device for multi-core instruction-set simulation
US8352924B2 · kind B2 · utility
2Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Oct 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.